The semiconductor integrated circuit (IC) industry has experienced rapid growth. Technological advances in IC materials and design have produced generations of ICs where each generation has smaller and more complex circuits than the previous generation. These advances have increased the complexity of processing and manufacturing ICs and, for these advances to be realized, similar developments in IC processing and manufacturing are needed. In the course of IC evolution, functional density (i.e., the number of interconnected devices per chip area) has generally increased while geometry size (i.e., the smallest component (or line) that can be created using a fabrication process) has decreased. This scaling down process generally provides benefits by increasing production efficiency and lowering associated costs. Such scaling down also presents critical challenges for manufacturing and processing IC devices having gate stacks. For example, as metal-oxide-semiconductor field-effect transistors (MOSFETs) are scaled down through various technology nodes, high-k/metal gate stacks have been implemented. Capacitance equivalent thickness (CET) scaling of the high-k dielectric material can improve high-k/metal gate device performance. However, it has been observed that CET values for the high-k material are increased by growth of an interfacial layer of the high-k/metal gate stack during processing, such as during thermal processes. Accordingly, although existing high-k/metal gate stacks and methods of manufacturing such high-k/metal gate stacks have been generally adequate for their intended purposes, as device scaling down continues, they have not been entirely satisfactory in all respects.